Reducing noise effects in electrostatic discharge circuits
AssigneeTexas Instruments Incorporated
InventorsBenjamin Lee Amey, Sigfredo Emanuel Gonzalez Diaz
Life of this patent
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Abstract
A DPI circuit reduces noise effects in an ESD circuit when coupled between an ESD circuit and a protected pin. The DPI circuit includes an NMOS transistor coupled between an output node and a lower rail and a charge pump coupled between the input node and the gate of the first NMOS transistor. A resistor is coupled between the gate of the first NMOS transistor and the lower rail.
Claims21
A direct power injection (DPI) circuit for reducing noise effects in an electrostatic discharge (ESD) circuit coupled to a protected pin, the DPI circuit comprising:
- an output node for coupling to the gate of a complementary metal oxide silicon (CMOS) power device that is coupled to carry an ESD event on the protected pin to ground when turned ON;
- an input node for coupling to the protected pin;
- a first N-type metal oxide silicon (NMOS) transistor having a drain coupled to the output node, a source coupled to a lower rail and a gate;
- a charge pump circuit coupled between the input node and the gate of the first NMOS transistor;
- and
- a first resistor having a first terminal coupled to the gate of the first NMOS transistor and a second terminal coupled to the lower rail.
A system on a chip (SOC) comprising:
- a driver coupled to provide an output signal on a protected pin;
- a complementary metal oxide silicon (CMOS) power device coupled between the protected pin and a lower rail and having a gate;
- and
- a direct power injection (DPI) circuit comprising:
- an output node coupled to the gate of the CMOS power device;
- an input node coupled to the protected pin;
- a first N-type metal oxide silicon (NMOS) transistor having a drain coupled to the output node, a source coupled to a lower rail and a gate;
- a charge pump circuit coupled between the input node and the gate of the first NMOS transistor;
- and
- a first resistor having a first terminal coupled to the gate of the first NMOS transistor and a second terminal coupled to the lower rail;
- and
- a second NMOS transistor having a drain coupled to the gate of the first NMOS transistor, a source coupled to the lower rail and a gate coupled to receive a disable signal.
A system on a chip (SOC) comprising:
- a transceiver driver coupled to provide differential output signals on a first protected pin and a second protected pin;
- a first electrostatic discharge (ESD) circuit coupled between the first protected pin and a lower rail;
- a second ESD circuit coupled between the second protected pin and the lower rail;
- and
- a direct power injection (DPI) circuit comprising:
- an output node coupled to the first and second ESD circuits;
- an input node coupled to the first protected pin and the second protected pin;
- a first NMOS transistor having a drain coupled to the output node, a source coupled to a lower rail and a third gate;
- a charge pump circuit coupled between the input node and the gate of the first NMOS transistor;
- and
- a first resistor having a first terminal coupled to the gate of the first NMOS transistor and a second terminal coupled to the lower rail.
Dependencies are inferred from the claim text.