Method of achieving robustness of the device in short circuit condition by adjusting the current limit threshold based repetitive fault condition

A process of operating a state machine controlling a power transistor, the power transistor providing current on a source and drain path to a load, and the power transistor having a gate, comprising:

• (a) entering a first state upon receiving an active reset signal, including de-asserting the transistor gate;
• (b) moving from the first state to a second state upon receiving an inactive reset signal, including enabling fault detection circuity;
• (c) moving from the second state to a third state upon receiving an active enable signal, including enabling digital core circuitry coupled to the transistor, starting a charge pump, and starting a first timer;
• (d) moving from the third state to a fourth state upon the first timer elapsing, including asserting the transistor gate to turn on the transistor in a nominal mode to supply specified current to the load, and starting a second timer;
• (e) moving from the fourth state to a fifth state in response to receiving an active fault signal from the fault detection circuitry, including de-asserting the transistor gate, and starting a third timer;
• (f) moving from the fifth state to a sixth state in response to the third timer elapsing and receiving an inactive fault signal from the fault detection circuitry, including maintaining de-asserting the transistor gate and starting a fourth timer;
• (g) moving from the sixth state to the fourth state in response to the fourth timer elapsing, including asserting the transistor gate to turn on the transistor in a nominal mode to supply specified current to the load, and starting the second timer.