Current steering circuit, corresponding device, system and method

A circuit, comprising:

• a current source circuit comprising:
• a first transistor and a second transistor having respective control terminals and current paths therethrough, the control terminal of the first transistor coupled to a first bias voltage node and the control terminal of the second transistor coupled to a second bias voltage node;
• a first electronic switch having a selectively activatable current path therethrough,
• wherein the current paths through the first and second transistor and the current path through the first electronic switch are cascaded in an output current line between a circuit output node and ground, the output current line having an intermediate portion between the first and second transistor with a charge transfer node in the intermediate portion;
• a second electronic switch arranged between a third bias voltage node and the charge transfer node;
• and
• a third electronic switch arranged between the charge transfer node and the control terminal of the second transistor;
• wherein the second electronic switch and the third electronic switch are selectively activatable to a conductive state to provide charge transfer current paths coupling the charge transfer node to the third bias voltage node or the second bias voltage node, respectively;
• and
• wherein the output current line provides an output current;
• and
• a driver circuit coupled to said current source circuit and configured to provide the control signal to selectively activate the first switch as well as activation signals to selectively activate the second switch and the third switch.

A circuit, comprising:

• a current source transistor having a control terminal biased by a first bias voltage;
• a cascode transistor having a control terminal biased by a second bias voltage;
• a first switching transistor having a control terminal coupled to receive a first digital control signal;
• wherein conduction paths of the current source transistor, cascode transistor and first switching transistor are coupled in series;
• a second switching transistor having a conduction path coupled between a third bias voltage and an intermediate node between the cascode transistor and the first switching transistor and having a control terminal coupled to receive a second digital control signal;
• and
• a third switching transistor having a conduction path coupled between the intermediate and the control terminal of the cascode transistor and having a control terminal coupled to receive a third digital control signal.