Comparator having differential fdsoi transistor pair with gate connected to back-gate to reduce rts noise

A comparator circuit structure comprising:

• a differential transistor pair including, a first transistor having a gate terminal, a drain terminal electrically connected to a first node, a fully depleted semiconductor on insulator (FDSOI) channel region positioned between a source terminal and the drain terminal, a back-gate terminal distinct from the gate terminal, separated from the FDSOI channel region with a buried insulator layer positioned beneath the FDSOI channel region, wherein the back-gate terminal of the first transistor and a first input signal voltage are electrically connected to the gate terminal of the first transistor, and the source terminal is electrically connected to a first shared node;
• a second transistor having a gate terminal, a source terminal electrically connected to the first shared node, a drain terminal electrically connected to a second node, a FDSOI channel region positioned between the source and drain terminal, and a buried insulator positioned beneath the FDSOI channel region and a back-gate terminal distinct from the gate terminal, wherein the back-gate terminal of the second transistor and a second input signal voltage are electrically connected to the gate terminal of the second transistor;
• a plurality of biasing current sink transistors electrically connected to the first shared node of the differential pair;
• and
• a plurality of load current source transistors electrically connected to the first and second node of the differential pair.

A method of operating a comparator, the method comprising:

• applying a first differential input voltage signal to a gate terminal of a first differential transistor, wherein the first differential transistor includes a drain terminal electrically connected to a first node, a fully depleted semiconductor on insulator (FDSOI) channel region positioned between a source terminal and the drain terminal, and a back-gate terminal distinct from the gate terminal separated from the FDSOI channel region with a buried insulator layer positioned beneath the FDSOI channel region, wherein the source terminal is electrically connected to a first shared node;
• connecting a source of a second differential transistor to the first shared node, wherein the second differential transistor including a gate, a drain terminal electrically connected to a second node, a FDSOI channel region positioned between the source and drain terminal, and a buried insulator positioned beneath the FDSOI channel region and a back-gate terminal distinct from the gate terminal, wherein a trench isolation forms an insulating barrier between the back-gate terminal and the gate terminal;
• applying a second differential input voltage signal to the gate terminal of the second differential transistor, wherein the first and second differential input voltage signals have a first level of Random Telegraph Signal (RTS) noise;
• and
• adjusting the transconductance of the first and second differential transistor by coupling the back-gate terminals of the first and second differential transistor to the respective gate terminals of the first and second differential transistors, wherein adjusting the transconductance reduces the RTS noise to a second level.