Digital measurement circuit and memory system using the same

A digital measurement circuit comprising:

• a first input flip-flop configured to receive a first signal and a first clock signal, and output a second signal;
• a second input flip-flop configured to receive the second signal and a second clock signal, and output a third signal, the second clock signal being an inverted signal of the first clock signal;
• and
• a delay line configured to receive and delay the second signal, and output the delayed second signal as first through n-th output signals,
• wherein the second signal is enabled at a rising time of the first clock signal, and the third signal is enabled at a falling time of the first clock signal.

A memory system comprising:

• a clock generator configured to provide an internal clock signal;
• a memory cell array configured to store data;
• an input/output driver configured to receive the internal clock signal from the clock provider, and input or output the data stored in the memory cell array based on the internal clock signal;
• and
• the clock generator comprises,
• a duty measuring circuit configured to generate a first signal at a rising time of the internal clock signal,
• delay the first signal by ΔT through n*(ΔT),
• output each the delayed first signals which are delayed by ΔT through n*(ΔT) respectively, and
• measure a high pulse width of the internal clock signal using the delayed first signals.