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US 2019/0199332 A1Published application
Parasitic capacitance cancellation using dummy transistors
AssigneeTexas Instruments Incorporated
InventorsBasavaraj G. GORGUDDI, Ani XAVIER
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Abstract
In some examples, an apparatus includes a plurality of first transistors coupled to a first input terminal and a first output terminal. The apparatus also includes a plurality of second transistors coupled to a second input terminal and a second output terminal. The apparatus further includes a plurality of first dummy transistors coupled to the first input terminal and the second output terminal. The apparatus also includes a plurality of second dummy transistors coupled to the second input terminal and the first output terminal.
Claims17
An apparatus, comprising:
- a plurality of first transistors coupled to a first input terminal and a first output terminal;
- a plurality of second transistors coupled to a second input terminal and a second output terminal;
- a plurality of first dummy transistors coupled to the first input terminal and the second output terminal;
- and
- a plurality of second dummy transistors coupled to the second input terminal and the first output terminal;
- wherein the plurality of first transistors share a first interdigitated n-type doped region with the plurality of first dummy transistors;
- wherein the plurality of first transistors share a second interdigitated n-type doped region with the plurality of second dummy transistors;
- wherein the plurality of second transistors share a third interdigitated n-type doped region with the plurality of second dummy transistors;
- and
- wherein the plurality of second transistors share a fourth interdigitated n-type doped region with the plurality of first dummy transistors.
7 more elements
A system comprising:
- a first switch comprising a first parasitic capacitor;
- a second switch comprising a second parasitic capacitor;
- a first dummy switch comprising a first dummy capacitor;
- a second dummy switch comprising a second dummy capacitor,
- a first input metal layer coupled to sources of the first switch and the first dummy switch;
- a second input metal layer coupled to sources of the second switch and the second dummy switch;
- a first output metal layer coupled to drains of the first switch and the second dummy switch;
- and
- a second output metal layer coupled to drains of the second switch and the first dummy switch;
- wherein the sources of the first switch and the first dummy switch share a first interdigitated n-type doped region;
- wherein the sources of the second switch and the second dummy switch share a second interdigitated n-type doped region;
- wherein the drains of the first switch and the second dummy switch share a third interdigitated n-type doped region;
- and
- wherein the drains of the second switch and the first dummy switch share a fourth interdigitated n-type doped region.
11 more elements
17-20. (canceled)
Dependencies are inferred from the claim text.