Resistive memory with amorphous silicon filaments
AssigneeInternational Business Machines Corporation
InventorsAlexander Reznicek, Bahman Hekmatshoartabari
Life of this patent
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Abstract
A method for manufacturing a semiconductor memory device includes forming a first silicon layer on a bottom conductive layer, transforming the first silicon layer into a first polysilicon layer, forming a second silicon layer stacked on the first polysilicon layer, and a third silicon layer stacked on the second silicon layer, transforming the second and third silicon layers into second and third polysilicon layers, wherein the first and third polysilicon layers have a first doping type, and the second polysilicon layer has a second doping type different from the first doping type, forming an amorphous silicon layer on the third polysilicon layer, and forming a top conductive layer on the amorphous silicon layer.
Claims20
A semiconductor memory device, comprising:
- a plurality of wordlines spaced apart from each other;
- a plurality of stacked structures spaced apart from each other and formed on each wordline of the plurality of wordlines;
- wherein each of the plurality of stacked structures comprises:
- a first polysilicon layer on a wordline of the plurality of wordlines;
- a second polysilicon layer on the first polysilicon layer;
- a third polysilicon layer on the second polysilicon layer;
- and
- an amorphous silicon layer on the third polysilicon layer;
- wherein the first and third polysilicon layers have a first doping type, and the second polysilicon layer has a second doping type different from the first doping type;
- and
- a plurality of bitlines spaced apart from each other and formed on the plurality of stacked structures;
- wherein the plurality of bitlines are oriented perpendicularly with respect to the plurality of wordlines.
A semiconductor memory device, comprising:
- a plurality of wordlines spaced apart from each other;
- a plurality of stacked structures spaced apart from each other and formed on each wordline of the plurality of wordlines;
- wherein each of the plurality of stacked structures comprises:
- a bipolar diode on a wordline of the plurality of wordlines;
- and
- an amorphous silicon resistive memory element on the bipolar diode;
- and
- a plurality of bitlines spaced apart from each other and formed on the plurality of stacked structures;
- wherein the plurality of bitlines are oriented perpendicularly with respect to the plurality of wordlines;
- and
- wherein the plurality of stacked structures are parts of a memory cell array having a three-dimensional (3D) cross-point structure.
A semiconductor memory device, comprising:
- a memory cell array comprising a plurality of memory cells defined by a plurality of wordlines and a plurality of bitlines oriented perpendicularly with respect to the plurality of wordlines;
- wherein a memory cell of the plurality of memory cells comprises:
- a bipolar diode on a wordline of the plurality of wordlines;
- and
- an amorphous silicon resistive memory element on the bipolar diode;
- and
- wherein the memory cell array has a three-dimensional (3D) cross-point structure.
Dependencies are inferred from the claim text.