Non-planar gate thin film transistor

An integrated circuit, comprising:

• a substrate;
• and
• a first one of a source or drain formed above the substrate;
• a second one of the source or drain formed above the first one of the source or drain;
• and
• a hole formed through the first one of the source or drain and the second one of the source or drain;
• and
• a semiconductive layer formed on a sidewall of the hole.

A system, comprising:

• a processor;
• and
• at least one of a network device, a display, or a memory coupled to the processor;
• wherein the processor includes an integrated circuited circuit, the integrated circuit including:
• a plurality of layers formed on a substrate, the plurality of layers including a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD;
• a semiconductive layer formed on a sidewall of the plurality of layers;
• and
• a gate dielectric layer formed on the semiconductive layer;
• and
• a gate formed in contact with the gate dielectric layer.

A method of producing an integrated circuit, the method comprising:

• forming a first one of a source or drain above a substrate;
• forming an inter-layer dielectric (ILD) above the first one of the source or drain;
• forming a second one of the source or drain above the ILD, wherein at least a portion of the second one of the source or drain is formed over the first one of the source or drain;
• forming a hole in the portion of the second one of the source or drain;
• forming a semiconductive layer on a sidewall of the hole;
• forming a gate dielectric layer disposed in the hole and on the semiconductive layer;
• and
• forming a gate disposed in the hole after the formation of the gate dielectric layer.