Programmable Charge Storage Transistor, An Array Of Elevationally Extending Strings Of Memory Cells, And A Method Of Forming An Array Of Elevationally Extending Strings Of Memory Cells

A programmable charge-storage transistor comprising:

• channel material extending vertically or within 10° of vertical;
• insulative charge-passage material;
• charge-storage material;
• a control gate;
• and
• charge-blocking material between the charge-storage material and the control gate, the charge-blocking material comprising:
• a non-ferroelectric insulator material;
• a ferroelectric insulator material;
• and
• the ferroelectric insulator material and the non-ferroelectric insulator material being directly against one another, the ferroelectric insulator material being thinner than the non-ferroelectric insulator material.

An array of elevationally-extending strings of memory cells, comprising:

• a stack comprising vertically-alternating insulative tiers and wordline tiers, the wordline tiers comprising control-gate material having terminal ends corresponding to control-gate regions of individual memory cells,
• charge-storage material of the individual memory cells extending elevationally along individual of the control-gate regions;
• charge-blocking material of the individual memory cells extending elevationally along the individual control-gate regions between the charge-storage material and the individual control-gate regions, the charge-blocking material comprising:
• a non-ferroelectric insulator material;
• and
• a ferroelectric insulator material;
• transistor channel material of the individual memory cells extending elevationally along the charge-storage material;
• and
• insulative charge-passage material extending elevationally along the charge-storage material between the transistor channel material and the charge-storage material.

A method of forming an array of elevationally-extending strings of memory cells, the method comprising:

• forming a stack comprising vertically-alternating tiers of different composition first and second materials, the first material being insulative;
• forming elevationally-extending channel openings into the alternating tiers;
• forming first charge-blocking insulator material in the channel openings elevationally along the alternating tiers;
• forming charge-storage material in the channel openings elevationally along the alternating tiers and the first charge-blocking insulator material;
• forming insulative charge-passage material in the channel openings elevationally along the alternating tiers and the charge-storage material;
• forming transistor channel material in the channel openings elevationally along the alternating tiers and the insulative charge-passage material;
• removing at least some of the second material from the stack;
• forming second charge-blocking insulator material laterally proximate the first charge-blocking insulator material, the second charge-blocking insulator material being of different composition from that of the first charge-blocking insulator material, one of the first charge-blocking insulator material or the second charge-blocking insulator material comprising a non-ferroelectric insulator material, the other of the first charge-blocking insulator material or the second charge-blocking insulator material comprising a ferroelectric insulator material;
• and
• forming control-gate material laterally over the second charge-blocking insulator material, the control-gate material having terminal ends corresponding to control-gate regions of individual memory cells.