Formation of a bottom source-drain for vertical field-effect transistors

A method of forming a bottom source-drain layer of a vertical field-effect transistor component, the method comprising:

• forming an anchor structure on a substrate such that the substrate comprises a first anchor region, a second anchor region, and a middle region located there between;
• depositing a sacrificial layer on the middle region of the substrate;
• depositing a channel layer on the sacrificial layer;
• depositing a fin layer on the channel layer and on the anchor structure;
• forming a patterned mandrel layer on the fin layer;
• depositing a sidewall spacer layer on the patterned mandrel layer and the fin layer;
• forming a plurality of vertical fins from the sidewall spacer layer;
• wherein the plurality of vertical fins comprise the sidewall spacer layer, the fin layer, and the channel layer;
• wherein the plurality of vertical fins span the middle region from the first anchor region to the second anchor region;
• wherein the forming exposes the sacrificial layer;
• depositing an oxide liner and performing a liner etch back of the oxide liner;
• removing the sacrificial layer such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate;
• and
• depositing the bottom source-drain layer such that the bottom source-drain layer fills in the gap.