Power silicon carbide based mosfet transistors with improved short circuit capabilities and methods of making such devices
AssigneeCree, Inc.
InventorsQingchun Zhang, Alexander V. Suvorov
Life of this patent
Estimating the term…
Abstract
A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
Claims21
A power MOSFET, comprising:
- a silicon carbide drift region having a first conductivity type;
- a first well region located in an upper portion of the silicon carbide drift region and extending to an upper surface of the silicon carbide drift region, the first well region doped with second conductivity dopants and at least a lower portion of the first well region having a second conductivity type, where the second conductivity type is different than the first conductivity type;
- a second well region located in the upper portion of the silicon carbide drift region and extending to the upper surface of the silicon carbide drift region, the second well region spaced apart from the first well region to define a JFET region of the silicon carbide drift region, the second well region doped with second conductivity dopants and at least a lower portion of the second well region having the second conductivity type;
- and
- a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type,
- wherein a depth of the first well region is at least 1.5 microns, and
- wherein the depth of the first well region exceeds a distance between the first and second well regions.
(canceled)
A power MOSFET, comprising:
- a silicon carbide drift region having a first conductivity type;
- a first well region located in an upper portion of the silicon carbide drift region and extending to an upper surface of the silicon carbide drift region, the first well region doped with second conductivity dopants and at least a lower portion of the first well region having a second conductivity type, where the second conductivity type is different than the first conductivity type;
- a second well region located in the upper portion of the silicon carbide drift region and extending to an upper surface of the silicon carbide drift region, the second well region doped with second conductivity dopants and at least a lower portion of the second well region having a second conductivity type, the first and second well regions defining a JFET region therebetween;
- a gate insulating layer on the upper surface of the first well region;
- and
- a channel region under the gate insulating layer in a side portion of the first well region, an upper portion of the channel region having the first conductivity type,
- wherein a doping density of the silicon carbide drift region, a width of the JFET region, a doping density of the channel region and/or a depth of the first well region are selected to produce a negative temperature coefficient for the drain current for at least temperatures in the range of 25-150° C. at drain-source currents of less than 40 Amps.
19-28. (canceled)
Dependencies are inferred from the claim text.