Vertical transistors having improved gate length control using uniformly deposited spacers

A method of forming a semiconductor device, the method comprising:

• forming a channel fin structure across from a major surface of a substrate, wherein the channel fin structure comprises a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing;
• forming an initial gate structure over the plurality of channel fins;
• forming spacers along vertical sidewall portions of the initial gate structure, each of the spacers having a predetermined spacer height dimension, wherein a thickness dimension of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing;
• and
• subsequent to forming the spacers along the vertical sidewall portions of the initial gate structure, removing portions of the initial gate structure where the vertical sidewall portions of the initial gate structure are not covered by the spacers to define a plurality of gate structures each having a gate structure height dimension defined by the spacer height dimension;
• wherein a gate length dimension of each of the plurality of gate structures comprises the gate height dimension.