Managing Gate Coupling For Memory Devices

A semiconductor memory device comprising:

• a semiconductor substrate including active regions protruding therefrom, adjacent active regions defining trenches therebetween;
• an isolation layer formed on the semiconductor substrate and in the trenches;
• floating gates formed on corresponding active regions, each floating gate having a lower floating gate and an upper floating gate that are sequentially stacked, the lower floating gate having a smaller width than the upper floating gate and a substantially same center line as the upper floating gate;
• an inter-gate dielectric layer on top surfaces of the floating gates and on the isolation layer, the inter-gate dielectric layer defining gaps between adjacent floating gates, and
• a control gate electrode on top of the floating gates and in the gaps of the dielectric layer,
• wherein at least one of the gaps has a bottom surface being between a top surface and a bottom surface of the lower floating gate of one of the floating gates, and a space between sidewalls of the lower floating gate and the inter-gate dielectric layer in the gap is filled with a material of the isolation layer.

A method of fabricating a semiconductor device, the method comprising:

• providing a physical layer on a semiconductor substrate, the layer having a lower layer and an upper layer that are sequentially stacked, the lower layer including a first material and the upper layer including a second material that has at least one property different from the first material;
• forming a protective pattern on the layer;
• and
• controlling an etching process to etch the layer, such that the first material has a different etching rate than the second material during the etching process and the lower layer has a different dimension than the upper layer after the etching process, the lower layer and the upper layer having a same center line.