Field effect transistor with controllable resistance
AssigneeInternational Business Machines Corporation
InventorsYulong Li, Paul M. Solomon, Siyuranga Koswatta
Life of this patent
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Abstract
Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.
Claims25
A method for forming a semiconductor device, the method comprising:
- forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate, the source terminal and the drain terminal formed on either side of a channel region by recessing the substrate;
- forming an energy barrier adjacent to the source terminal and the channel region by etching the energy barrier in recesses formed by the recessing;
- and
- forming a conductive gate over the channel region.
A method for forming a semiconductor device, the method comprising:
- forming a source terminal of a semiconductor fin on a substrate;
- forming an energy barrier on a surface of the source terminal;
- forming a channel on a surface of the energy barrier;
- forming a drain terminal on a surface of the channel;
- recessing the drain terminal and the channel on either sides of the channel;
- etching the energy barrier in recesses formed by the recessing;
- recessing the source terminal using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier;
- forming a first bottom spacer on a surface of the source terminal and a sidewall of the semiconductor fin;
- and
- forming a gate stack on the surface of the first bottom spacer.
A semiconductor device comprising:
- a source terminal;
- a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;
- an energy barrier adjacent to the source terminal and the channel region;
- and
- a conductive gate stack formed over the channel region.
A semiconductor device comprising:
- a semiconductor fin formed on a substrate, the semiconductor fin comprising an energy barrier between a source terminal and a channel region of the semiconductor fin;
- a conductive gate over the channel region of the semiconductor fin;
- and
- a bottom spacer between the conductive gate and the substrate.
A semiconductor device comprising:
- a semiconductor fin formed on a substrate, the semiconductor fin comprising:
- a source terminal that is doped using a first dopant;
- a drain terminal that is doped using a second dopant at a first concentration;
- and
- a channel that is doped using the second dopant at a second concentration;
- wherein the second concentration is lower than the first concentration.
Dependencies are inferred from the claim text.