Field effect transistor with reduced contact resistance

An FET transistor comprising at least:

• a semiconductor portion of which a first part forms a channel of the FET transistor;
• a gate which at least partly surrounds the first part of the semiconductor portion;
• internal dielectric spacers arranged around doped second parts of the semiconductor portion between which the first part of the semiconductor portion is arranged and which form extension regions of the FET transistor;
• electrically conductive portions in contact with doped surfaces of extremities of the semiconductor portion and with doped surfaces of third parts of the semiconductor portion, forming part of source and drain regions of the FET transistor, at least partly surrounding the third parts of the semiconductor portion, with each of the second parts of the semiconductor portion being arranged between the first part of the semiconductor portion and one of the third parts of the semiconductor portion,
• wherein the first part, the second parts, the extremities, and the third parts are all formed from a same material that forms the semiconductor portion.