US 2019/0198615 A1Published application

Iii-nitride devices including a graded depleting layer

AssigneeTransphorm Inc.

InventorsUmesh Mishra, Rakesh K. Lal, Geetak Gupta, Carl Joseph Neufeld, David Rhodes

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Abstract

A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

Claims24

Dependent claims

A transistor, comprising:

a III-N layer structure comprising a III-N channel layer and a III-N barrier layer;
a 2DEG channel in the III-N channel layer;
a source and a drain;
a gate between the source and the drain, the gate being over the III-N layer structure;
and
a graded III-N layer contacting the III-N barrier layer which is at least partially in an access region between the gate and the drain;
wherein
a grading profile of the graded III-N layer causes holes to be induced in at least a portion of the graded III-N layer without p-type dopants being included in the portion of the graded III-N layer;
and
the grading profile of the graded III-N layer is selected such that mobile charge in the 2DEG channel in an access region between the gate and the drain is depleted while the gate is biased relative to the source at a voltage lower than a transistor threshold voltage and the drain is biased above a minimum voltage relative to the source, but not depleted while the gate is biased relative to the source at a voltage lower than the transistor threshold voltage and the drain is biased below the minimum voltage relative to the source.

7 more elements

A depletion mode transistor, comprising:

a III-N layer structure comprising a III-N barrier layer adjacent to a III-N channel layer, a 2DEG channel in the III-N channel layer;
a source electrode and a drain electrode, wherein the source electrode and drain electrode are electrically connected to the 2DEG channel;
a graded III-N layer over the III-N layer structure, the graded III-N layer having a first side adjacent to the III-N layer structure and a second side opposite the first side;
and
a p-doped III-N layer over the graded III-N layer, the p-doped III-N layer having a third side contacting the second side of the graded III-N layer and a fourth side opposite the third side;
a gate electrode directly contacting the p-doped III-N layer between the source electrode and the drain electrode;
wherein
a composition of the graded III-N layer is graded such that the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side;
an area of the third side of the p-doped III-N layer is less than an area of the second side of the graded III-N layer;
and
the graded III-N layer is electrically isolated from the source electrode and the drain electrode.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/287,211Filed 27 Feb 2019
Priority: 31 May 2016
Published: 27 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 62/125
Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions: shapes of junctions between the…
H10D 8/60
Diodes: schottky-barrier diodes
H10D 30/015
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
H10D 30/4738
Using Group III-V semiconductor material: having multiple donor layers

Family

Application62/343,782Us provisional application · filed 31 May 2016
Application15/564,498Division · filed 5 Oct 2017
Application16/287,211Division
US 10,224,401 B2Related patent
US 10,629,681 B2Related patent
US 2018/0158909 A1Published application
US 2019/0198615 A1This patent

From the US filing history. Foreign family members aren’t listed.