Power Semiconductor Device Having an SOI Island
AssigneeInfineon Technologies AG
InventorsAlexander Philippou, Anton Mauder
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Abstract
A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.
Claims9
A power semiconductor device, comprising a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device, wherein the insulation structure comprises:
- a sidewall laterally confining the semiconductor region;
- a bottom vertically confining the semiconductor region;
- and
- a local deepening forming at least a part of a transition between the sidewall and the bottom,
- wherein the local deepening extends further along an extension direction as compared to the bottom.
A power semiconductor device, comprising:
- a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between the terminals, the first load terminal comprising a first metallization arranged above a surface of the semiconductor body, the first metallization being laterally confined by at least one first flank;
- a plurality of power cells, each power cell of the plurality of power cells comprising:
- a semiconductor channel region arranged in contact to the drift region and forming a pn-junction with the drift region;
- and
- a trench including an insulator and an insulated control electrode configured to control a path of the load current in the channel region, the trench extending from a surface of the semiconductor body along an extension direction;
- a control terminal configured to provide a control signal to the control electrode, the control terminal comprising a second metallization arranged above the surface, the second metallization being laterally confined by at least one second flank;
- and
- a semiconductor-on-insulator-island arranged in the semiconductor body and separate from each of the plurality of power cells,
- wherein each of the at least one first flank and the at least one second flank overlap in a lateral direction with the semiconductor-on-insulator island.
Dependencies are inferred from the claim text.