Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element

A semiconductor structure, comprising:

• a plurality of vertical field-effect transistors (VFETS) disposed on a substrate;
• and
• a plurality of resistive elements disposed over top surfaces of the VFETs;
• wherein each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell;
• wherein the VFETs are arranged in two or more columns and two or more rows;
• wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region;
• wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate;
• and
• wherein top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs.

An integrated circuit comprising:

• a resistive random access memory (ReRAM) device comprising a plurality of ReRAM cells, each of the plurality of ReRAM cells comprising:
• a given one of a plurality of vertical field-effect transistors (VFETs) disposed on a substrate;
• and
• a given one of a plurality of resistive elements disposed over a top surface of the given VFET;
• wherein the VFETs are arranged in two or more columns and two or more rows;
• wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region;
• wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate;
• and
• wherein top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs.