Multiple vertical tft structures for a vertical bit line architecture

A method for fabricating a non-volatile memory, comprising:

• forming a set of vertical TFTs above a substrate, the set of vertical TFTs includes a first TFT and a second TFT spaced apart by a first separation distance, the set of vertical TFTs includes a third TFT spaced apart from the second TFT by a second separation distance greater than the first separation distance;
• etching back a first layer of oxide to expose a portion of the set of vertical TFTs;
• depositing a layer of titanium nitride with a thickness that is greater than half of the first separation distance and less than half of the second separation distance;
• etching the layer of titanium nitride by at least the thickness in a vertical direction orthogonal to the substrate;
• depositing an alternating stack of conducting layers and dielectric layers above the set of vertical TFTs;
• etching a plurality of memory holes extending through the alternating stack of conducting layers and dielectric layers;
• depositing one or more memory element layers within the plurality of memory holes;
• and
• depositing a second conducting material within the plurality of memory holes.

A memory structure, comprising:

• a first set of memory cells;
• a second set of memory cells;
• a set of vertical TFTs arranged above a substrate, the set of vertical TFTs includes a first TFT and a second TFT separated by a first separation distance in a horizontal dimension and a third TFT separated from the second TFT by a second separation distance greater than the first separation distance in the horizontal dimension, the set of vertical TFTs includes a fourth TFT separated from the third TFT by the first separation distance in the horizontal dimension;
• a first vertical bit line connected to the first set of memory cells, the first vertical bit line connected to a first layer of titanium nitride that electrically shorts a drain-side end of the first TFT with a drain-side end of the second TFT;
• and
• a second vertical bit line connected to the second set of memory cells, the second vertical bit line connected to a second layer of titanium nitride that electrically shorts a drain-side end of the third TFT with a drain-side end of the fourth TFT.