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US 2019/0198530 A1Published application
Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorsToshio HINO, Junji IWAHORI
Life of this patent
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Abstract
The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.
Claims8
A semiconductor integrated circuit device comprising:
- a first standard cell including a three-dimensional transistor device, the first standard cell being a logic cell;
- and
- a second standard cell including a three-dimensional transistor device, the second standard cell being a capacitor cell, wherein
- the first standard cell includes:
- a first three-dimensional diffusion layer extending in a first direction, the first three-dimensional diffusion layer being one three-dimensional diffusion layer or a plurality of three-dimensional diffusion layers arranged in a second direction perpendicular to the first direction;
- and
- a first local interconnect extending in the second direction, and connecting the first three-dimensional diffusion layer and a power supply interconnect together, the power supply interconnect extending in the first direction and supplying a predetermined first power supply voltage,
- the second standard cell includes:
- a second three-dimensional diffusion layer extending in the first direction, the second three-dimensional diffusion layer being one three-dimensional diffusion layer or a plurality of three-dimensional diffusion layers arranged in the second direction;
- a second local interconnect extending in the second direction and connecting the second three-dimensional diffusion layer and the power supply interconnect together;
- and
- a gate interconnect extending in the second direction so as to intersect with the second three-dimensional diffusion layer in plan view, surrounding the second three-dimensional diffusion layer, and provided with a predetermined second power supply voltage,
- a length of a portion, of the second local interconnect, which protrudes from the second three-dimensional diffusion layer in a direction away from the power supply interconnect in the second standard cell is greater than a length of a portion, of the first local interconnect, which protrudes from the first three-dimensional diffusion layer in a direction away from the power supply interconnect in the first standard cell,
- the second standard cell further includes:
- a third three-dimensional diffusion layer extending in the first direction, the third three-dimensional diffusion layer being one three-dimensional diffusion layer or a plurality of three-dimensional diffusion layers arranged in the second direction,
- the third three-dimensional diffusion layer is provided on an opposite side of the power supply interconnect from the second three-dimensional diffusion layer, and
- the gate interconnect passes under the power supply interconnect, extends to intersect with the third three-dimensional diffusion layer in plan view, and surrounds the third three-dimensional diffusion layer.
14 more elements
A semiconductor integrated circuit device comprising:
- a standard cell which is a capacitor cell, wherein
- the standard cell includes:
- a first power supply interconnect extending in a first direction and supplying a first power supply voltage;
- a second power supply interconnect extending in the first direction and supplying a second power supply voltage;
- a capacitor provided between the first power supply interconnect and the second power supply interconnect, and including a three-dimensional transistor device;
- a first interconnect supplying the second power supply voltage to the capacitor;
- and
- a second interconnect supplying the first power supply voltage to the capacitor,
- the first and second power supply interconnects and the first and second interconnects are provided in a same metal interconnect layer,
- the first interconnect includes:
- a first portion extending in the first direction and adjacent to the first power supply interconnect, the first portion being an interconnect closest to the first power supply interconnect in the same metal interconnect layer;
- a second portion extending in the first direction and adjacent to the second power supply interconnect, the second portion being an interconnect closest to the second power supply interconnect in the same metal interconnect layer;
- and
- a third portion extending in a second direction perpendicular to the first direction and connecting the first portion and the second portion together.
11 more elements
Dependencies are inferred from the claim text.