Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorYasuhiro SHIMURA
Life of this patent
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Abstract
A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
Claims17
A semiconductor memory device comprising:
- a laminated body including a plurality of control gate electrodes laminated in a first direction, and having longitudinally a second direction intersecting with the first direction;
- a first insulation separating layer arranged along the laminated body and having longitudinally the second direction;
- a plurality of semiconductor layers having longitudinally the first direction, having a peripheral area surrounded by the plurality of control gate electrodes, and arranged in a plurality of rows within the laminated body, the plurality of rows being arranged in a third direction intersecting with the first direction and the second direction, the plurality of semiconductor layers including a first semiconductor layer positioned in a first row and a second semiconductor layer positioned in a second row, the first row being closer to the first insulation separating layer than the second row;
- a first memory portion disposed between the control gate electrode and the first semiconductor layer;
- a second memory portion disposed between the control gate electrode and the second semiconductor layer;
- a plurality of bit lines extending in the third direction, the plurality of bit lines including a first bit line connected with the first semiconductor layer and a second bit line connected with the second semiconductor layer;
- and
- a control circuit configured to control a voltage applied to the bit lines, wherein
- the control circuit, during a reading operation for reading data from the first memory portion and data from the second memory portion, applies a first voltage to the first bit line and applies a second voltage smaller than the first voltage to the second bit line.
A semiconductor memory device comprising:
- a plurality of laminated bodies each including a plurality of control gate electrodes laminated in a first direction;
- a first insulation separating layer extending in the second direction intersecting the first direction and arranged between the laminated bodies adjacent in the third direction intersecting the first and second directions;
- a plurality of semiconductor layers extending in the first direction within the laminated body and including a first semiconductor layer and a second semiconductor layer, the first semiconductor layer being closer to the first insulation separating layer than the second semiconductor layer;
- a first memory portion disposed between the control gate electrode and the first semiconductor layer;
- a second memory portion disposed between the control gate electrode and the second semiconductor layer;
- a plurality of bit lines including a first bit line connected to the first semiconductor layer and a second bit line connected to the second semiconductor layer;
- and
- a control circuit configured to control a voltage applied to the bit lines, wherein
- the control circuit, during a reading operation for reading data from the first memory portion and data from the second memory portion, applies a first voltage to the first bit line and applies a second voltage smaller than the first voltage to the second bit line.
Dependencies are inferred from the claim text.