Three-dimensional memory device containing multi-threshold-voltage drain select gates and method of making the same

A method of forming a three-dimensional memory device, comprising:

• forming an alternating stack of insulating layers and spacer material layers located over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
• forming a plurality of rows of memory stack structures through the alternating stack, wherein each of the memory stack structures comprises charge storage elements located at levels of the electrically conductive layers and laterally surrounding a respective vertical semiconductor channel, wherein at least one of the electrically conductive layers comprises a first select gate electrode for multiple rows of memory stack structures within the plurality of rows, and at least another of the electrically conductive layers comprise a second select gate electrode for the multiple rows of memory stack structures;
• and
• locally modifying threshold voltages for the first and second select gate electrodes for the memory stack structures, wherein:
• a first row of memory stack structures among the multiple rows of memory stack structures has a higher threshold voltage for the first select gate electrode than a second row of memory stack structures among the multiple rows of memory stack structures has for the first select gate electrode;
• and
• the first row of memory stack structures has a lower threshold voltage for the second select gate electrode than the second row of memory stack structures has for the second select gate electrode.

A three-dimensional NAND memory device comprising:

• an alternating stack of insulating layers and electrically conductive word line layers located over a substrate;
• at least one first drain select gate electrode located over the alternating stack, and extending through a first drain select transistor and a second drain select transistor;
• at least one second drain select gate electrode located between the first drain select electrode and the alternating stack, and extending through a third drain select transistor and a fourth drain select transistor;
• wherein:
• the first drain select transistor and the third drain select transistor are located in a first NAND memory string;
• the second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string;
• the first drain select transistor has a higher threshold voltage than the second drain select transistor;
• and
• the third drain select transistor has a lower threshold voltage than the fourth drain select transistor.