Cell disturb prevention using a leaker device to reduce excess charge from an electronic device
AssigneeMicron Technology, Inc.
InventorDurai Vishak Nirmal Ramaswamy
Life of this patent
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Abstract
Various embodiments comprise apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.
Claims20
An apparatus, comprising:
- multiple electronic devices, at least a portion of each electronic device of the multiple electronic devices having a bottom electrode that is at least partially electrically isolated from the bottom electrodes of the other electronic devices;
- and
- a resistive interconnect electrically coupled to two or more of the bottom electrodes, the resistive interconnect being configured to discharge at least a portion of excess charge from the two or more bottom electrodes.
A method comprising:
- forming multiple electronic devices, each device of the multiple electronic devices having at least one electrode;
- and
- forming a leaker device to electrically couple at least a portion of the electrodes of the multiple electronic devices, the leaker device to drain at least a portion of excess charge from the at least a portion of the electrodes.
An apparatus, comprising:
- multiple memory cells disposed in rows and columns, each memory cell of the multiple memory cells having a bottom electrode at least partially electrically isolated from the bottom electrodes of other memory cells of the multiple memory cells;
- multiple leaker devices each comprising a resistive interconnect, wherein one of the multiple leaker devices is coupled to each of the bottom electrodes within a respective row of the multiple memory devices, each leaker device being configured to discharge at least a portion of excess charge from the bottom electrodes to prevent a memory cell disturb, while not electrically shorting respective ones of the bottom electrodes;
- and
- a contact line electrically coupling each of the multiple leaker devices to a discharge structure.
Dependencies are inferred from the claim text.