Memory Arrays, and Methods of Forming Memory Arrays

A memory array, comprising:

• a vertical stack of alternating insulative levels and wordline levels;
• channel material extending vertically along the stack;
• gates along the wordline levels;
• memory cell structures along the wordline levels and located between the gates and the channel material;
• the memory cell structures including charge-storage regions and charge-blocking regions;
• the charge-blocking regions being between the charge-storage regions and the gates;
• voids along the insulative levels;
• individual of the voids each comprising a first region between a pair of vertically-neighboring of the gates and a second region between a pair of vertically-neighboring of the charge-storage regions;
• and
• insulative liners within the voids and along outer peripheries of the voids.

A method of forming an assembly, comprising:

• forming a first opening through a stack of alternating first and second levels;
• the first levels comprising first material, and the second levels comprising second material;
• recessing the second material of the second levels along the first opening to form first gaps;
• the first gaps being vertically between segments of the first levels;
• forming first protective structures within the first gaps;
• recessing the first material of the first levels along the first opening to form second gaps;
• the second gaps being vertically between segments of the first protective structures;
• utilizing oxidizing conditions to oxidize edges of the first material of the first levels along the second gaps and to oxidize edges of the first protective structures along the first opening;
• the oxidized edges of the first material being charge-blocking regions, and being along remaining portions of the first material of the first levels;
• the oxidized edges of the first protective structures being ledges;
• third gaps being vertically between the ledges;
• forming charge-trapping regions within the third gaps and along the charge-blocking regions;
• removing the ledges to leave fourth gaps, the fourth gaps being vertically between the charge-trapping regions;
• forming second protective structures within the fourth gaps and directly adjacent the first protective structures;
• forming vertically-extending tunneling material within the first opening, the tunneling material extending along edges of the second protective structures and along the charge-trapping regions;
• forming channel material within the first opening and adjacent the tunneling material;
• forming a second opening through the stack, with the second opening extending through the remaining portions of the first material of the first levels;
• removing the remaining portions of the first material of the first levels to form cavities along the second opening;
• forming conductive regions within the cavities;
• and
• removing the second material of the second levels, the first protective structures, and the second protective structures to form voids.