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US 2019/0198507 A1Published application
Semiconductor memory device
AssigneeRenesas Electronics Corporation
InventorsKoji NII, Makoto YABUUCHI
Life of this patent
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Abstract
To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.
Claims19
A semiconductor memory device comprising:
- a plurality of memory cells;
- and
- a word line coupled to the plurality of memory cells,
- wherein the word line is extended in a first direction, and
- wherein each of the plurality of memory cells includes a gate electrode extended along a second direction intersecting with the first direction.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory cells;
- a word line coupled to the memory cells;
- and
- a plurality of bit lines coupled to the memory cells,
- wherein the word line is arranged to extend in a first direction,
- wherein the plurality of bit lines are arranged to extend in a second direction intersecting with the first direction,
- wherein each of the memory cells includes a plurality of gate electrodes extended in the second direction,
- wherein each of the memory cells includes six MOS transistors, and
- wherein the two of the six MOS transistors are arranged next to each other in the first direction.
6 more elements
A semiconductor memory device comprising:
- a first word line and a second word line provided along a first direction;
- a first bit line, a second bit line, and a third bit line provided along a second direction intersecting with the first direction;
- a first memory cell coupled to the first word line, the first bit line, and the second bit line;
- and
- a second memory cell coupled to the second word line, the second bit line, and the third bit line,
- wherein each of the first memory cell and the second memory cell has a gate electrode extended in the second direction.
3 more elements
Dependencies are inferred from the claim text.