Semiconductor memory device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei YAMAZAKI, Yasuhiko TAKEMURA
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Abstract
The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
Claims25
(canceled)
A semiconductor memory device comprising:
- a driver circuit;
- an insulating layer over the driver circuit;
- and
- a memory cell over the insulating layer, the memory cell comprising:
- a transistor;
- and
- a capacitor overlapping with and electrically connected to the transistor,
- wherein the capacitor comprising a first layer comprising a first conductive material and a second layer comprising a second conductive material,
- wherein the first layer comprises a first portion and a second portion,
- wherein the second layer comprises a portion,
- wherein the portion of the second layer is sandwiched between the first portion and the second portion in a horizontal direction, and
- wherein the memory cell is electrically connected to the driver circuit.
A semiconductor memory device comprising:
- a driver circuit;
- an insulating layer over the driver circuit;
- and
- a memory cell over the insulating layer, the memory cell comprising:
- a transistor;
- and
- a capacitor overlapping with and electrically connected to the transistor,
- wherein a channel region of the transistor comprises an oxide semiconductor material,
- wherein a gate electrode of the transistor comprises copper, and
- wherein the memory cell is electrically connected to the driver circuit.
A semiconductor memory device comprising:
- a driver circuit;
- a multilayer wiring layer over the driver circuit, the multilayer wiring layer comprising a wiring which comprises copper;
- and
- a memory cell over the multilayer wiring layer, the memory cell comprising:
- a transistor;
- and
- a capacitor overlapping with and electrically connected to the transistor,
- wherein the capacitor comprising a first layer comprising a first conductive material and a second layer comprising a second conductive material,
- wherein the first layer comprises a first portion and a second portion,
- wherein the second layer comprises a portion,
- wherein the portion of the second layer is sandwiched between the first portion and the second portion in a horizontal direction, and
- wherein the memory cell is electrically connected to the driver circuit through the wiring.
Dependencies are inferred from the claim text.