Layout Method
AssigneeSamsung Electronics Co., Ltd.
InventorsIn Wook OH, Jae Seok YANG, Jong Hyun LEE, Hyun Jae LEE, Sung Wook HWANG
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.
Claims16
A layout method, the method comprising:
- forming circuit active fin lines and circuit gate lines to intersect the circuit active fin lines in a layout region;
- identifying a vacant region in the layout region;
- setting a grid map in the vacant region using a grid unit;
- and
- forming dummy active fin lines and dummy gate lines within the grid map using a cell unit,
- wherein the grid unit has a quadrangular shape having first and second sides opposing each other and third and fourth sides opposing each other, and
- wherein the cell unit includes an active fin unit connecting middle portions of the first and second sides of the grid unit to each other, and a gate unit connecting middle portions of the third and fourth sides of the grid unit to each other and intersecting the active fin unit.
A layout method, the method comprising:
- forming first circuit active fin lines and first circuit gate lines intersecting the first circuit active fin lines in a layout region, the first circuit active fin lines being formed at a first pitch and the first circuit gate lines being formed at a second pitch;
- identifying a vacant region in the first layout region;
- setting a grid map in the vacant region;
- and
- forming dummy active fin lines and dummy gate lines in the vacant region in which the grid map is set,
- wherein setting the grid map includes forming a plurality of grid units, and arranging the plurality of grid units in the vacant region,
- wherein forming the dummy active fin lines and the dummy gate lines includes forming a plurality of cell units by interposing a cell unit between the plurality of grid units,
- wherein the cell unit includes an active fin unit and a gate unit intersecting each other;
- and
- wherein an intersection region of the active fin unit and the gate unit of the cell unit is disposed in a central portion of the grid unit.
-35. (canceled)
Dependencies are inferred from the claim text.