Semiconductor device for enhancing electrostatic discharge protection and layout structure thereof

A layout structure of a semiconductor device for enhancing electrostatic discharge protection, and the semiconductor device comprising:

• an electrostatic discharge protection device;
• and
• a device with small feature linewidth located on same well region as the electrostatic discharge protection device, the device with small feature linewidth being located at a middle portion, and the electrostatic discharge protection device being disposed on both sides of the device with small feature linewidth;
• and the layout structure comprising:
• a plurality of gate polysilicon including a gate of the electrostatic discharge protection device and a gate of the device with small feature linewidth, each gate polysilicon having a long strip structure, and respective gate polysilicon being arranged in lateral direction at intervals, wherein width direction of the gate polysilicon is the lateral direction;
• a plurality of N type doping regions disposing between adjacent, acting as a N type source region of the electrostatic discharge protection device and a N type drain region of the electrostatic discharge protection device arranged in lateral direction at intervals;
• a metal layer comprising:
• a first metal layer forming as interdigitated structure, and being configured to connect the N type source region of the electrostatic discharge protection device with a N type source region of the device with small feature linewidth;
• and
• a second metal layer forming as interdigitated structure, and being configured to connect the N type drain region of the electrostatic discharge protection device with N type drain region of the device with small feature linewidth.