Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits

An integrated circuit comprising:

• a first active region and a second active region, each extending on a substrate in a first horizontal direction, wherein the first active region and the second active region are in parallel to each other and have conductivity types different from each other;
• a first gate line that extends in a second horizontal direction that crosses the first horizontal direction, wherein the first gate line forms a first transistor with the first active region, and wherein the first transistor comprises a gate configured to receive a first input signal;
• a second gate line that extends in the second horizontal direction and that forms a second transistor with the second active region, the second transistor comprising a gate configured to receive a second input signal;
• and
• a third gate line that extends in the second horizontal direction between the first and second gate lines, and that comprises a first partial gate line and a second partial gate line, wherein the first partial gate line forms a third transistor with the first active region, wherein the second partial gate line forms a fourth transistor with the second active region, wherein the third transistor comprises a gate configured to receive the second input signal, and wherein the fourth transistor comprises a gate configured to receive the first input signal;
• a first source/drain contact extending in the second horizontal direction and having a bottom surface connected to drain regions of the first and third transistors;
• and
• a second source/drain contact extending in the second horizontal direction and having a bottom surface connected to drain regions of the second and fourth transistors,
• wherein the first and second source/drain contacts are electrically connected to each other on a region between the first and second active regions.

An integrated circuit comprising:

• a first active region and a second active region, each extending on a substrate in a first horizontal direction in parallel to each other, wherein the first active region and the second active region have conductivity types different from each other;
• a first gate line extending in a second horizontal direction that crosses the first horizontal direction, the first gate line comprising a first partial gate line and a second partial gate line, wherein the first partial gate line forms a first transistor with the first active region and the second partial gate line forms a second transistor with the second active region, wherein the first transistor comprises a gate configured to receive a first input signal, and the second transistor comprises a gate configured to receive a second input signal;
• and
• a second gate line extending in the second horizontal direction and comprising a third partial gate line and a fourth partial gate line, wherein the third partial gate line forms a third transistor with the first active region and the fourth partial gate line forms a fourth transistor with the second active region, wherein the third transistor comprises a gate configured to receive the second input signal and the fourth transistor comprises a gate configured to receive the first input signal,
• wherein the first and second partial gate lines are spaced apart from each other in the second horizontal direction, and
• wherein the third and fourth partial gate lines are spaced apart from each other in the second horizontal direction.