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US 2019/0198478 A1Published application
Fan out package and methods
AssigneeIntel IP Corporation
InventorsLizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
Life of this patent
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Abstract
A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
Claims17
A semiconductor device, comprising:
- a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die;
- and
- a molded routing layer coupled to the integrated routing layer, wherein the molded routing layer includes a second width that is wider than the first width.
A electronic system, comprising:
- a processor die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die;
- a molded routing layer coupled to the integrated routing layer, wherein the molded routing layer includes a second width that is wider than the first width;
- a circuit board coupled to the molded routing layer;
- and
- a memory device coupled to the circuit board, wherein the circuit board is configured to route communications between the processor die and the memory device.
2 more elements
17-22. (canceled)
Dependencies are inferred from the claim text.