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US 2019/0198453 A1Published application
Semiconductor device and method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorHiroaki SEKIKAWA
Life of this patent
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Abstract
It is prevented that reliability of a semiconductor device is reduced due to advancement of cracking or chipping within a substrate from a scribe region side to a circuit region side of a semiconductor chip. A dummy isolation part is formed from the upper surface to an intermediate depth of the substrate in a peripheral region that is a part of a scribe region adjacent to a seal ring region, and is not cut during dicing. The dummy isolation part having a DTI structure is disposed so as to surround the circuit region and the seal ring region.
Claims16
A semiconductor device, comprising:
- a semiconductor substrate having a first region, a second region surrounding the first region in plan view, and a third region surrounding the first region in plan view;
- a plurality of elements formed in the vicinity of an upper surface of the semiconductor substrate in the first region, and configuring a circuit;
- an element isolation part buried in a first trench formed in the upper surface of the semiconductor substrate, and isolating the elements from one another;
- a first interconnection formed over the semiconductor substrate in the second region with an interlayer insulating film in between, and configuring no circuit;
- a first conductive coupling part coupled to the first interconnection while penetrating the interlayer insulating film in the second region, and configuring no circuit;
- and
- a third trench formed in the upper surface of the semiconductor substrate in the third region, and having a deeper depth than the first trench,
- wherein each of the first interconnection, the first conductive coupling part, and the third trench is formed annually surrounding the first region in plan view.
5 more elements
A method of manufacturing a semiconductor device, the method comprising the steps of:
- (a) providing a semiconductor substrate having a plurality of first regions, a plurality of second regions surrounding the respective first regions in plan view, and a plurality of third regions surrounding the respective first regions in plan view;
- (b) forming an element isolation part buried in a first trench formed in an upper surface of the semiconductor substrate in the first region;
- (c) forming a plurality of elements formed in the vicinity of the upper surface of the semiconductor substrate in the first region;
- (d) after the step (c) and the step (b), forming a first interlayer insulating film over the semiconductor substrate;
- (e) forming a second trench in the upper surface of the semiconductor substrate in the first region, the second trench penetrating the first interlayer insulating film and having a deeper depth than the first trench, and forming a third trench in the upper surface of the semiconductor substrate in the third region, the third trench penetrating the first interlayer insulating film, having a deeper depth than the first trench, and surrounding the first region in plan view;
- (f) forming a second interlayer insulating film covering the third trench over the semiconductor substrate, thereby forming a third interlayer insulating film including the first interlayer insulating film and the second interlayer insulating film;
- (g) forming a third trench penetrating the third interlayer insulating film in the first region, and forming a fourth trench penetrating the third interlayer insulating film in the second region, and surrounding the first region in plan view;
- (h) forming a first conductive coupling part buried in the third trench and configuring a circuit, and forming a second conductive coupling part buried in the fourth trench and configuring no circuit;
- and
- (i) cutting the semiconductor substrate in a fourth region between the third regions separately adjacent to each other, thereby forming a semiconductor chip including the first region, the second region, and the third region.
7 more elements
Dependencies are inferred from the claim text.