Multi-chip package with high density interconnects

An apparatus comprising:

• a plurality of organic dielectric layers forming a substrate;
• a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate;
• a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate;
• a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate;
• and
• a plurality of second conductive interconnects disposed within the substrate to couple a first linearly arranged grouping of the plurality of second conductive contacts associated with a first die site with a first linearly arranged grouping of the plurality of second conductive contacts associated with a second die site and to couple a second linearly arranged grouping of the plurality of second conductive contacts associated with the first die site with a second linearly arranged grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first linearly arranged groupings are present in a layer of the substrate above the conductive interconnects to couple the second linearly arranged groupings along an imaginary reference line orthogonal to the top surface of the substrate.

A system comprising:

• a display subsystem;
• a wireless communication interface;
• and
• a multi-chip package, the multi-chip package comprising:
• one or more processor dies;
• one or more memory dies;
• and
• a substrate coupled with the processor and memory dies, wherein the substrate comprises:
• top surface contacts arranged as coupling sites for the processor and memory dies, wherein at least one coupling site contains at least a first contact pitch and a second contact pitch higher than the first contact pitch;
• bottom surface contacts at a third contact pitch, wherein the third contact pitch is lower than the first contact pitch;
• and
• interconnects embedded within organic dielectric material, wherein the interconnects couple some of the top surface contacts with the bottom surface contacts and couple linearly arranged groupings of the top surface contacts having the second contact pitch along sides of a plurality of coupling sites with linearly arranged groupings of the top surface contacts along sides of adjacent coupling sites, wherein the interconnects further couple inner linearly arranged groupings of top surface contacts of adjacent coupling sites by extending deeper within the organic dielectric material.

A method comprising:

• forming a substrate on a peelable carrier, the substrate comprising:
• a plurality of organic dielectric layers;
• a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate;
• a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate;
• a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate;
• and
• a plurality of second conductive interconnects disposed within the substrate to couple a first linearly arranged grouping of the plurality of second conductive contacts associated with a first die site with a first linearly arranged grouping of the plurality of second conductive contacts associated with a second die site and to couple a second linearly arranged grouping of the plurality of second conductive contacts associated with the first die site with a second linearly arranged grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first linearly arranged groupings are present in a layer of the substrate above the conductive interconnects to couple the second linearly arranged groupings along an imaginary reference line orthogonal to the top surface of the substrate;
• and
• attaching integrated circuit dies to the die sites on the substrate.