US 2019/0198442 A1Published application

Feol/Beol Heterogeneous Integration

AssigneeSarda Technologies, Inc.

InventorWilliam E. Batchelor

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Abstract

Devices and methods are described for fabricating field effect transistors (FET) using compound semiconductor front end of line (FEOL) integrated with back end of line (BEOL) technologies for applications including power management and communications. Wafer-level FEOL processing with a minimum number of thin interconnects may be used to produce multiple chiplets, which are small, high current density functional building blocks. Chiplets may have tight source/drain finger pitch, high gate width per area, and minimum lateral current flow, to reduce resistance, FEOL process complexity, and cost. Panel-level BEOL processing may serve as an inexpensive extension of FEOL processes. BEOL may form multiple interconnect layers and via bars with progressively increasing thickness and cross section area. These BEOL interconnects and via bars connect together the parallel chiplets, handle lateral flow of high current and reduce electrical and thermal resistance the FETs to increase current carrying capacity of the FETs.

Claims21

Dependent claims

A gallium arsenide device comprising:

a front end of line portion fabricated on a gallium arsenide substrate, the front end of line portion including:
an active region comprising:
a plurality of drain ohmic fingers and plurality of source ohmic fingers alternating with the drain fingers,
gate fingers disposed between the drain fingers and the source fingers,
a gate metal layer including the gate fingers disposed on the substrate,
a first passivation layer disposed over the substrate and gate metal layer, the first passivation layer including source vias disposed over the plurality of source ohmic fingers and drain vias disposed over the plurality drain ohmic fingers, and
a metal 1 layer including:
source metal 1 fingers disposed on the plurality of source ohmic fingers and within the plurality of source vias, and
drain metal 1 fingers disposed on the plurality of drain ohmic fingers and within the drain vias;
and
a non-active region disposed between active regions of the substrate, the non-active region comprising:
a length of gate metal conductor disposed on the substrate and contiguous laterally with the gate fingers,
a gate interconnect via about the length of the gate metal conductor disposed in the first passivation layer, on a portion of the gate metal conductor,
the metal 1 layer further comprising:
a metal 1 gate conductor at least the length of the gate metal conductor and disposed on a portion of width of the gate metal conductor including the gate interconnect via, the gate interconnect via providing electrical interconnection between the gate metal 1 conductor and the gate metal conductor, and
a source metal 1 conductor about the length of the gate metal conductor and disposed on the first passivation layer contiguous laterally with the plurality of source fingers, and
a second passivation layer disposed over the active and non-active regions, including the metal 1 layer, the second passivation layer including a second source interconnect via about the length of the gate metal conductor and disposed over a portion of the width the source metal 1 conductor, the second passivation layer not including vias for providing interconnection to source fingers in the active region.

14 more elements

A gallium arsenide device comprising:

a gallium arsenide substrate comprising:
alternating drain ohmic fingers and source ohmic fingers disposed within the substrate, and
gate fingers disposed between the drain fingers and the source fingers, the source ohmic fingers, drain ohmic fingers, and gate fingers form an active region of the gallium arsenide device,
a gate metal layer comprising:
a gate metal conductor disposed on a non-active region between adjacent active regions, and
gate metal fingers disposed on the gate fingers in the active region, the gate metal fingers in direct electrical contact with the gate metal conductor;
a first passivation layer disposed on the substrate and gate metal layer, the first passivation layer comprising:
source vias disposed over the source ohmic fingers,
drain vias disposed over the drain ohmic fingers, and
a gate via disposed within the non-active region over the gate metal conductor;
a metal 1 layer disposed on the first passivation layer, the metal 1 region comprising:
source metal 1 fingers disposed on the first passivation layer and in electrical communication with the source ohmic fingers through the source vias,
a source metal 1 conductor disposed on the first passivation layer within the non-active region and in direct electrical contact with the source metal 1 fingers,
drain metal 1 fingers disposed on the first passivation layer and in electrical communication with the drain ohmic fingers through the drain vias,
a drain metal 1 conductor disposed on the first passivation layer within the non-active region and in direct electrical contact with the drain metal 1 fingers, and
a gate metal 1 conductor disposed on the first passivation layer within the non-active region and in direct electrical contact with the gate metal through the gate via;
a second passivation layer disposed on the first passivation layer and the metal 1 layer, the second passivation layer comprising:
a source via 2 disposed within the non-active region and over the source metal 1 conductor,
a drain via 2 disposed within the non-active region and over the drain metal 1 conductor, and
a gate a via 2 disposed within the non-active region and over the gate metal 1 conductor.

17 more elements

The gallium arsenide device 9, further comprising a metal 2 layer disposed on the via 2 layer, the metal 2 layer comprising:

a source metal 2 conductor disposed on the second passivation layer and in electrical communication with the source metal 1 conductor through the source via 2,
a drain metal 2 conductor disposed on the second passivation layer and in electrical communication with the drain metal 1 conductor through the drain via 2, and.
a gate metal 2 conductor disposed on the second passivation layer and in electrical communication with the gate metal 1 conductor through the gate via 2.

A method for fabricating a device, the method comprising:

fabricating ohmic fingers in an active region of a gallium arsenide substrate, the ohmic fingers comprising:
alternating drain ohmic fingers and source ohmic fingers disposed within the substrate, and
gate fingers disposed between the drain fingers and the source fingers;
fabricating a gate metal layer using a front end of line (FEOL) process, the gate metal layer comprising:
a gate metal conductor disposed on a non-active region between adjacent active regions of ohmic fingers, and
gate metal fingers disposed on the gate fingers in the active region, the gate metal fingers in direct electrical contact with the gate metal conductor;
fabricating a first passivation layer on the substrate and gate metal layer using FEOL, the first passivation layer comprising:
source vias disposed over the source ohmic fingers,
drain vias disposed over the drain ohmic fingers, and
a gate via disposed within the non-active region over the gate metal conductor;
fabricating a metal 1 layer on the first passivation layer using FEOL processes, the metal 1 region comprising:
source metal 1 fingers disposed on the first passivation layer and in electrical communication with the source ohmic fingers through the source vias,
a source metal 1 conductor disposed on the first passivation layer within the non-active region and in direct electrical contact with the source metal 1 fingers,
drain metal 1 fingers disposed on the first passivation layer and in electrical communication with the drain ohmic fingers through the drain vias,
a drain metal 1 conductor disposed on the first passivation layer within the non-active region and in direct electrical contact with the drain metal 1 fingers, and
a gate metal 1 conductor disposed on the first passivation layer within the non-active region and in direct electrical contact with the gate metal through the gate via;
fabricating a second passivation layer on the first passivation layer and the metal 1 layer using FEOL processes, the second passivation layer comprising:
a source via 2 disposed within the non-active region and over the source metal 1 conductor,
a drain via 2 disposed within the non-active region and over the drain metal 1 conductor, and
a gate a via 2 disposed within the non-active region and over the gate metal 1 conductor.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/228,345Filed 20 Dec 2018
Priority: 21 Dec 2017
Published: 27 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10W 20/43
Characterised by their conductive parts: layouts of interconnections
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 62/85
Characterised by the materials: being Group III-V materials, e.g. GaAs
H10D 64/01
Electrodes of devices having potential barriers: manufacture or treatment