Overlay error and process window metrology

A method for inspection during semiconductor wafer fabrication, comprising:

• forming a plurality of test structures on a semiconductor wafer along two opposite directions, wherein each of the test structures comprises a target feature and a sample feature formed over the target feature, wherein an offset distance between the sample feature and the target feature of each of the test structures increases gradually along the two opposite directions;
• producing an image of the test structures by applying an electron beam over the test structures;
• performing image analysis of the image to recognize two boundary positions at which a particular gray level is displayed;
• and
• calculating a process window according to the two boundary positions.

A wafer inspecting apparatus for inspecting a semiconductor wafer comprising:

• a plurality of test structures arranged along two opposite directions, wherein each of the test structures comprises a target feature and a sample feature formed over the target feature, wherein an offset distance between the sample feature and the target feature of each of the test structures increases gradually along the two opposite directions, the apparatus comprising:
• a stage assembly configured to hold the semiconductor wafer;
• a charged particle source positioned over the stage assembly and configured to emit an electron beam over the test structures;
• a detector positioned over the stage assembly and configured to receive secondary electrons from the test structures and produce image according to the detected secondary electrons;
• and
• a signal processor connected to the detector and configured to recognize a current center position at which a minimum gray level or a maximum gray level is displayed in the image.