US 2019/0198401 A1 · METHOD OF MANUFACTURING A CMOS TRANSISTOR

Abstract

A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.

Claims13

Dependent claims

A semiconductor device, comprising:

a plurality of isolation regions formed in a semiconductor substrate;
a gate insulating film formed on the semiconductor substrate;
a first gate electrode pattern formed on the gate insulating film;
a second gate electrode pattern formed adjacent to the first gate electrode pattern;
a p-type well region formed below the first gate electrode pattern, wherein the p-type well region is formed deeper than the plurality of isolation regions;
an n-type well region formed below the second gate electrode pattern, wherein the n-type well region is formed deeper than the plurality of isolation regions;
sidewall spacers formed at respective sidewalls of each of the first gate electrode pattern and the second gate electrode pattern;
a p-type source region and a p-type drain region formed in the n-type well region;
and
an n-type source region and an n-type drain region formed in the p-type well region,
wherein a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the isolation regions.

8 more elements

Dependencies are inferred from the claim text.

Method of manufacturing a cmos transistor

Life of this patent

Method of manufacturing a cmos transistor

Life of this patent

Abstract

Claims13