Junction formation in thick-oxide and thin-oxide vertical fets on the same chip

A semiconductor device, comprising:

• a plurality of vertical transistors on a substrate, wherein each of the plurality of vertical transistors comprises:
• a channel region extending vertically from the substrate, wherein the channel region includes a junction portion extending vertically from a bottom of the channel region;
• a bottom source/drain region on the substrate and around a lower portion of the channel region;
• a gate structure on the bottom source/drain region, wherein the gate structure comprises a gate oxide layer;
• and
• a top source/drain region on the gate structure and extending from the channel region;
• wherein a junction portion corresponding to a first vertical transistor of the plurality of vertical transistors extends to a greater height above a corresponding bottom source/drain region of the first vertical transistor than a junction portion corresponding to a second vertical transistor of the plurality of vertical transistors.

A method for manufacturing a semiconductor device, comprising:

• forming a first plurality of channel regions in a first device region on a substrate;
• forming a second plurality of channel regions in a second device region on the substrate;
• forming bottom source/drain regions on the substrate and around lower portions of each of the first and second plurality of channel regions in the first and second device regions;
• forming a dummy spacer layer on the bottom source/drain region in the first device region, wherein the dummy spacer layer includes one or more dopants;
• and
• forming a plurality of junction portions in the first and second plurality of channel regions in the first and second device regions;
• wherein the plurality of junction portions in the first device region extend to a greater height above the bottom source/drain regions than the plurality of junction portions in the second device region.