Assembly for 3d circuit with superposed transistor levels
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsFrancois ANDRIEU, Lamine Benaissa, Laurent Brunet
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Abstract
Fabrication of a circuit with superposed transistors, comprising assembly of a structure comprising transistors formed from a first semiconducting layer with a support (100) provided with a second semiconducting layer (102) in which transistors are provided on a higher level (N2), the second semiconducting layer (102) being coated with a thin layer (101) of silicon oxide, the assembly of said structure and the support (100) being made by direct bonding in which the thin silicon oxide layer (101) is bonded to oxidised portions (37b, 37c) of getter material.
Claims18
A method of making a circuit with superposed transistors comprising:
- a) providing a structure comprising at least one lower level of one or several transistors with a channel region formed in a first semiconducting layer supported on a substrate, said transistors being covered with at least one insulating layer in which one or several connection elements are formed, said structure being coated with one or several zones made of a given oxygen getter material capable of oxidising,
- b) assembling said structure with a support provided with at least one second semiconducting layer in which one or several channels of one or several higher level transistors are provided, the second semiconducting layer being coated with a thin layer of silicon oxide, particularly SiO2,
- the assembly of said structure and the support being made by bonding, the thin silicon oxide layer being brought into contact with and bonded to oxidised portions of said one or several areas of said given oxygen getter material, so as to make a bonding interface between portions of oxide of said given getter material and the thin silicon oxide layer.
The method of making a circuit with superposed transistors comprising:
- a) providing a structure comprising at least one lower level of one or several transistors with a channel region formed in a first semiconducting layer supported on a substrate, said transistors being covered with at least one insulating layer in which one or several connection elements are formed, said structure being coated with one or several zones made of a given oxygen getter material capable of oxidising,
- b) assembling said structure with a support provided with at least one second semiconducting layer in which one or several channels of one or several higher level transistors are provided, the second semiconducting layer being coated with a thin layer of silicon oxide, particularly SiO2,
- assembly of said structure and the support comprising the following steps:
- annealing under an oxidising atmosphere so as to form oxidised portions of said one or several areas of said given oxygen getter material, and
- bonding, in which the thin layer of silicon oxide is bonded to said oxidised portions, so as to make a bonding interface between oxide portions of said give getter material and the thin layer of silicon oxide.
Dependencies are inferred from the claim text.