Methods of fabricating integrated circuit devices
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-gyo CHUNG, Yun-seung KANG, Soung-hee LEE, Ji-seung LEE, Hyun-chul LEE
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Abstract
Methods of fabricating an integrated circuit device are provided. The methods may form feature patterns on a substrate using a quadruple patterning technology (QPT) process including one photolithography process and two double patterning processes. Sacrificial spacers obtained by first double patterning process and spacers obtained by second double patterning process may be formed on a feature layer at an equal level.
Claims24
A method of fabricating an integrated circuit device, the method comprising:
- forming a layer on a substrate, the layer comprising a first material;
- forming a pair of sacrificial spacers defining a sacrificial spacer recess between the pair of sacrificial spacers, wherein the sacrificial spacer recess exposes a portion of the layer, and wherein the pair of sacrificial spacers comprise the first material;
- forming a spacer layer comprising a plurality of first portions and a second portion, wherein each of the plurality of first portions of the spacer layer extends on a respective one of sidewalls of the pair of sacrificial spacers, and the second portion of the spacer layer overlaps the portion of the layer, and wherein the spacer layer comprises a second material that is different from the first material;
- forming a protective pattern overlapping the second portion of the spacer layer;
- removing upper portions of the protective pattern, upper portions of the spacer layer, and upper portions of the pair of sacrificial spacers to expose lower portions of the pair of sacrificial spacers;
- removing the lower portions of the pair of sacrificial spacers to expose a plurality of first etch regions of the layer while the protective pattern is overlapping the second portion of the spacer layer;
- removing the protective pattern to expose the second portion of the spacer layer;
- removing the second portion of the spacer layer to form a plurality of spacers and to expose a second etch region of the layer, wherein the plurality of spacers expose a plurality of etch regions of the layer, and the plurality of etch regions of the layer comprise the plurality of first etch regions and the second etch region of the layer;
- and
- etching the layer by using the plurality of spacers as an etch mask.
A method of fabricating an integrated circuit device, the method comprising:
- forming a layer on a substrate;
- forming a plurality of sacrificial spacers on the layer, wherein the plurality of sacrificial spacers expose a plurality of portions of the layer;
- forming a spacer layer comprising a plurality of first portions and a plurality of second portions, wherein each of the plurality of first portions extends on a respective one of sidewalls of the plurality of sacrificial spacers, and each of the plurality of second portions overlaps one of the plurality of portions of the layer, and wherein the spacer layer defines a plurality of spacer layer recesses, and one of the plurality of spacer layer recesses is between two adjacent ones of the plurality of sacrificial spacers;
- forming a plurality of protective patterns in the plurality of spacer layer recesses, respectively, wherein each of the plurality of protective patterns overlaps a respective one of the plurality of second portions of the spacer layer;
- removing upper portions of the spacer layer to expose the plurality of sacrificial spacers while the plurality of protective patterns is overlapping the plurality of second portions of the spacer layer, respectively;
- removing the plurality of sacrificial spacers to expose a plurality of first etch regions of the layer;
- removing the plurality of protective patterns to expose the plurality of second portions of the spacer layer;
- removing the plurality of second portions of the spacer layer to expose a plurality of second etch regions of the layer to form a plurality of spacers, wherein the plurality of second etch regions are spaced apart from the plurality of first etch regions, and each of the plurality of spacers comprises a portion of a respective one of the plurality of first portions of the spacer layer;
- and
- etching the plurality of first etch regions and the plurality of second etch regions of the layer by using the plurality of spacers as an etch mask.
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12-13. (canceled)
A method of fabricating an integrated circuit device, the method comprising:
- forming a layer on a substrate, wherein the layer comprises a first portion formed on a first region of the substrate and a second portion formed on a second region of the substrate, and wherein the layer comprises a first material;
- forming a blocking film extending on the second portion of the layer;
- forming a plurality of sacrificial spacers on the first portion of the layer and a first covering layer on the second portion of the layer, wherein the plurality of sacrificial spacers are spaced apart from each other and define a plurality of sacrificial spacer recesses exposing a plurality of exposed portions of the layer, respectively, wherein the plurality of sacrificial spacers comprise the first material, and wherein the first covering layer extends on at least a portion of the blocking film and comprises the first material;
- forming a spacer layer on the first portion of the layer and a second covering layer on the second portion of the layer, wherein the spacer layer comprises a plurality of first portions and a plurality of second portions, wherein each of the plurality of first portions of the spacer layer extends on a respective one of sidewalls of the plurality of sacrificial spacers, and each of the plurality of second portions of the spacer layer overlaps a respective one of the plurality of exposed portions of the layer, wherein the spacer layer defines a plurality of spacer layer recesses between two adjacent ones of the plurality of sacrificial spacers, and wherein the second covering layer extends on at least a portion of the first covering layer;
- forming a plurality of protective patterns in the plurality of spacer layer recesses, respectively, wherein one of the plurality of protective patterns overlaps one of the plurality of second portions of the spacer layer;
- removing upper portions of the spacer layer while the plurality of protective patterns is overlapping the plurality of second portions of the spacer layer;
- removing the plurality of sacrificial spacers to expose a plurality of first etch regions of the layer;
- removing the plurality of protective patterns to expose the plurality of second portions of the spacer layer;
- removing the plurality of second portions of the spacer layer to expose a plurality of second etch regions of the layer and to form a plurality of spacers, wherein the plurality of second etch regions are spaced apart from the plurality of first etch regions, and the plurality of spacers comprise portions of the plurality of first portions of the spacer layer, respectively;
- and
- etching the plurality of first etch regions and the plurality of second etch regions of the layer to form a plurality of patterns in the first region of the layer using the plurality of spacers as an etch mask while the blocking film is overlapping the second region of the layer.
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Dependencies are inferred from the claim text.