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US 2019/0198328 A1Published application
Multi-layer inter-gate dielectric structure and method of manufacturing thereof
AssigneeCypress Semiconductor Corporation
InventorsChun Chen, Shenqing Fang
Life of this patent
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Abstract
A memory device that has a first gate disposed adjacent to a second gate and a first dielectric structure disposed between the first and second gates. The first dielectric structure has at least four layers of oxide and nitride films arranged in an alternating layer, in which each of the at least four or more layers includes a width in an approximate range of 30 Å or less. The first dielectric structure further includes a top surface that is substantially un-etched.
Claims21
1-20. (canceled)
A semiconductor device, comprising:
- a substrate;
- a first gate structure having a first gate conducting layer and a first gate dielectric structure between the first gate conducting layer and the substrate;
- a second gate structure having a second gate conducting layer and a second gate dielectric structure between the second gate conducting layer and the substrate;
- and
- an inter-gate dielectric structure disposed between the first gate structure and the second gate structure, wherein the inter-gate dielectric structure includes four or more layers of two or more different dielectric films disposed in an alternating manner, and wherein each of the four or more layers includes a width in an approximate range of 30 Å or less.
2 more elements
A memory device, comprising:
- a first gate disposed adjacent to a second gate;
- and
- a first dielectric structure, disposed between the first and second gates, including at least four layers of oxide and nitride films arranged in an alternating layer, wherein each of the at least four or more layers oxide and nitride films includes a width in an approximate range of 30 Å or less, and wherein the first dielectric structure includes a top surface that is substantially un-etched.
Dependencies are inferred from the claim text.