US 2019/0198327 A1 · METAL CUT PATTERNING AND ETCHING TO MINIMIZE INTERLAYER DIELECTRIC LAYER LOSS

Abstract

The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.

Claims20

Dependent claims

An apparatus, comprising:

an interlayer dielectric layer formed on a substrate;
a first protective layer that covers:
a top portion associated with the interlayer dielectric layer, and
a trench region formed within the interlayer dielectric layer situated above the substrate;
a metal liner coating the first protective layer covering the trench region;
and
a second protective layer resistant to anisotropic metal etching and selective to the first protective layer so that the second protective layer is formed, due to selectivity of the second protective layer, on the first protective layer covering the top portion and is not formed, due to selectivity of the second protective layer, on the metal liner.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/290,306Filed 1 Mar 2019

Priority

18 Dec 2017

Published

27 Jun 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 64/01354
The insulator being formed after the semiconductor body, the semiconductor being silicon: passivation or protection of the electrode, e.g. using…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 64/01332
The insulator being formed after the semiconductor body, the semiconductor being silicon: making the insulator
H10D 64/691
Characterised by the insulator, e.g. by the gate insulator: comprising metallic compounds, e.g. metal oxides or metal silicates

Metal cut patterning and etching to minimize interlayer dielectric layer loss

Life of this patent

Metal cut patterning and etching to minimize interlayer dielectric layer loss

Life of this patent

Abstract

Claims20