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US 2019/0198250 A1Published application
Structure and methods of forming the structure
AssigneeMicron Technology, Inc.
InventorTae Heui Kwong
Life of this patent
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Abstract
Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. The dielectric does not cover a portion of the first conductor; and the second conductor does not cover the portion of the first conductor not covered by the dielectric.
Claims20
A semiconductor device comprising:
- a three-dimensional (3D) memory cell region;
- and
- a peripheral region adjacent to the memory cell region including a structure configured to provide capacitance for use during operation of the 3D memory cell region, the structure including:
- a first conductive level, a second conductive level above the first conductive level, and a third conductive level above the second conductive level, wherein the second conductive level is stepped back from an upper surface end portion of the first conductive level and the third conductive level is stepped back from an upper surface end portion of the second conductive level;
- and
- first and second dielectric levels, wherein the first dielectric level is disposed between the first and second conductive levels and does not cover at least a part of the upper surface end portion of the first conductive level, and wherein the second dielectric level is disposed between the second and third conductive levels and does not cover at least a portion of the upper surface end portion of the second conductive level.
3 more elements
An apparatus, comprising:
- a three-dimensional (3D) memory cell region;
- and
- a peripheral region adjacent to the memory cell region including a structure configured to provide capacitance for use during operation of the 3D memory cell region through multiple capacitors formed therein, wherein the multiple capacitors are formed by first, second, and third conductive levels arranged one above the other, wherein the conductive levels are separated from one another by first and second dielectric levels;
- and
- a charge pump region having a number of pump stages to supply at least one voltage to the 3D memory cell region through one or more contact electrodes electrically coupled to the 3D memory cell region.
2 more elements
A method of fabricating a memory device, the method comprising:
- forming a three-dimensional (3D) memory cell region including
- forming multiple word line levels each comprising a conductive material, the multiple word line levels respectively formed one above the other, and
- forming multiple dielectric levels, wherein one of the multiple dielectric levels is formed between a respective two adjacent word line levels;
- forming a peripheral region adjacent to the 3D memory cell region including
- forming a first conductive level, a second conductive level above the first conductive level, and a third conductive level above the second conductive level,
- removing portions of the second conductive level from an upper surface end portion of the first conductive level,
- removing portions of the third conductive level from an upper surface end portion of the second conductive level, and
- forming a first dielectric level between the first and second conductive levels,
- removing a portion of the first dielectric level to uncover at least a part of the upper surface end portion of the first conductive level,
- forming a second dielectric level between the second and third conductive levels, and
- removing a portion of the second dielectric level to uncover at least a portion of the upper surface end portion of the second conductive level;
- and
- forming a charge pump by forming at least two capacitive elements from at least some of the word line levels.
10 more elements
Dependencies are inferred from the claim text.