Memory circuit and testing method thereof
AssigneeNuvoton Technology Corporation
InventorCheng-Chih Wang
Life of this patent
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Abstract
A memory circuit and a testing method thereof are provided. The memory circuit includes multiple stage non-volatile memory (NVM) devices. An Nth stage NVM device includes a logic memory circuit, an NVM element, a write circuit and a read circuit. The logic memory circuit receives external data via a data input terminal in a normal mode and receives test data via a test input terminal in a test mode. The write circuit writes the test data or the external data to the NVM element during a writing period. The read circuit transmits stored data stored in the NVM element to an output terminal of the logic memory circuit during a reading period.
Claims16
A memory circuit comprising:
- M stage non-volatile memory devices coupled in series, wherein an Nth stage non-volatile memory device comprises:
- a logic memory circuit receiving external data via a data input terminal in a normal mode and receiving test data via a test input terminal in a test mode;
- a non-volatile memory element;
- a write circuit writing the test data or the external data to the non-volatile memory element during a writing period;
- and
- a read circuit transmitting stored data stored in the non-volatile memory element to an output terminal of the logic memory circuit during a reading period, wherein M is a positive integer greater than 2, N is a positive integer greater than 1, and M is greater than or equal to N.
A testing method comprising:
- disposing multiple stage non-volatile memory devices and coupling the non-volatile memory devices in series, wherein the non-volatile memory devices each comprises a non-volatile memory element;
- receiving test data in a test mode;
- writing the test data to the non-volatile memory element during a writing period;
- and
- during a reading period, outputting stored data stored in the non-volatile memory element.
Dependencies are inferred from the claim text.