Semiconductor apparatus and system relating to performing a high speed test in a low speed operation environment

A system comprising:

• an external apparatus configured to provide a first clock signal and reference data;
• a first semiconductor apparatus configured to generate a first internal clock signal from the first clock signal, and output the reference data as transmission data based on the first internal clock signal;
• and
• a second semiconductor apparatus configured to generate a second internal clock signal from the first clock signal, generate reception data by receiving the transmission data based on the second internal clock signal, and configured to generate an error detection signal based on the reference data and the reception data.

A method for testing a system including an external apparatus, a first semiconductor apparatus, and a second semiconductor apparatus, the method comprising:

• providing reference data to each of the first and second semiconductor apparatuses from the external apparatus;
• providing a first clock signal to the first semiconductor apparatus from the external apparatus, and generating a first internal clock signal from the first clock signal in the first semiconductor apparatus;
• providing a first clock signal to the second semiconductor apparatus from the external apparatus, and generating a second internal clock signal from the first clock signal in the second semiconductor apparatus;
• outputting the reference data to a shared bus based on the first internal clock signal in the first semiconductor apparatus;
• receiving the data transmitted through the shared bus, based on the second internal clock signal in the second semiconductor apparatus;
• and
• generating an error detection signal based on the received data and the reference data in the second semiconductor apparatus.