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US 2019/0198130 A1Published application
Test control circuit, semiconductor memory apparatus and semiconductor system using the test control circuit
AssigneeSK hynix Inc.
InventorHaeng Seon CHAE
Life of this patent
Estimating the term…
Abstract
A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.
Claims20
A test control circuit comprising:
- a control signal generation circuit configured to generate a normal set signal and a fast set signal based on a test command signal, a command pulse, and a fast access signal;
- a decoding circuit configured to generate a plurality of mode signals based on a plurality of the test command signals;
- and
- a test mode generation circuit configured to generate a normal test mode signal based on two or more mode signals and the normal set signal, and generate a fast test mode signal based on one mode signal and the fast set signal.
1 more element
A test control circuit comprising:
- a control signal generation circuit configured to generate a normal set signal based on a test command signal in a normal mode, and generate a fast set signal regardless of the test command signal in a fast access mode;
- and
- a test mode generation circuit configured to generate a normal test mode signal based on a mode signal, which is generated based on the test command signal, and the normal set signal in the normal mode, and generate a fast test mode signal based on the mode signal and the fast set signal in the fast access mode.
A test control circuit comprising:
- a test mode generation circuit configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal, and configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.
Dependencies are inferred from the claim text.