US 2019/0198126 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes a memory string with a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor connected in series. A first word line connects to the first memory cell, and a second word line connects to the second memory cell. Selection gates line are connected to first and second selection transistors. A control circuit is configured to control a write operation on the first memory string. The write operation includes a program loop with a program operation and a program verification operation. After the program loop is completed, a first voltage is applied to the first and second word lines and a second voltage is applied to the selection gate lines. The first voltage is sufficient to turn on the first and second memory cells. The second voltage is sufficient to turn on the selection transistors.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a first memory string including a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor connected in series;
a first word line connected to a gate of the first memory cell;
a second word line connected to a gate of the second memory cell;
a first selection gate line connected to a gate of the first selection transistor;
a second selection gate line connected to a gate of the second selection transistor;
and
a control circuit configured to control a write operation on the first memory string, wherein
the write operation includes:
a program loop including a program operation and a program verification operation on the first memory cell, and
after the program loop is completed, applying a first voltage to the first and second word lines and a second voltage to the first and second selection gate lines, the first voltage being sufficient to turn on the first and second memory cells, the second voltage being sufficient to turn on the first and second selection transistors.

7 more elements

A semiconductor memory device, comprising:

a first memory string including a first selection transistor, a first memory cell, a second memory cell, and selection transistor connected in series;
a first word line connected to a gate of the first memory cell;
a second word line connected to a gate of the second memory cell;
a first selection gate line connected to a gate of the first selection transistor;
a second selection gate line connected to a gate of the second selection transistor;
and
a control circuit configured to perform a write operation on the first memory string, the write operation including:
a program loop including a program operation and a program verification operation, the program loop being performed at least once on the first memory cell, the program loop being terminated when either the program verification operation verifies the first memory cell has an intended voltage value or a maximum number of program loop iterations has been reached;
and
a dummy read operation performed after the program loop has terminated, the dummy read operation comprising:
applying a first voltage to first and second word lines and a second voltage to the first and second selection gate lines, the first voltage being sufficient to turn on the first and second memory cells, the second voltage being sufficient to turn on the first and second selection transistors.

8 more elements

A method of controlling a write operation of a semiconductor memory device, the method comprising:

performing a program loop including a program operation and program verification operation executed in series on a first memory cell of a first memory string having a first selection transistor, the first memory cell, a second memory cell, and a second selection transistor connected in series;
and
after the program loop is completed, applying a first voltage to a first word line connected to a gate of the first memory and a second word line connected to a gate of the second memory cell and a second voltage to a first selection gate line connected to a gate of the first selection transistor and a second selection gate line connected to a gate of the second selection transistor, the first voltage being sufficient to turn on the first and second memory cells, the second voltage being sufficient to turn on the first and second memory cells, the second voltage being sufficient to turn on the first and second selection transistors.

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20