Semiconductor storage device
AssigneeToshiba Memory Corporation
InventorYusuke HIGASHI
Life of this patent
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Abstract
According to one embodiment, a semiconductor storage device includes: a first select transistor connected at a first end of a memory string; a second select transistor connected at a second end of the memory string; and a controller. In a write operation of writing data into a first memory cell transistor of the memory string, the controller performs: a first operation of applying a first voltage to a gate of the first memory cell transistor, while turning on the first and second select transistor; and a second operation of applying a second voltage higher than the first voltage to the gate of the first memory cell transistor, while turning off the first and second select transistor; and the second operation is performed after the first operation.
Claims20
A semiconductor storage device comprising:
- a memory cell transistor string including a plurality of memory cell transistors connected in series;
- a first select transistor connected at a first end of the memory cell transistor string;
- a second select transistor connected at a second end of the memory cell transistor string;
- and
- a controller,
- wherein:
- in a write operation of writing data into a first memory cell transistor of the memory cell transistor string, the controller performs:
- a first operation of applying a first voltage to a gate of the first memory cell transistor, while turning on the first select transistor and the second select transistor;
- and
- a second operation of applying a second voltage which is higher than the first voltage to the gate of the first memory cell transistor, while turning off the first select transistor and the second select transistor;
- and
- the second operation is performed after the first operation.
A semiconductor storage device comprising:
- a first memory cell transistor including a semiconductor, a ferroelectric disposed on the semiconductor, and a conductor disposed on the ferroelectric;
- and
- a controller,
- wherein:
- in a read operation, the controller applies an initialization voltage to a gate of the first memory cell transistor before applying a read voltage;
- and
- the initialization voltage has a polarity opposite to that of the coercive voltage of the ferroelectric, and has an absolute value smaller than that of the coercive voltage and greater than that of the read voltage.
Dependencies are inferred from the claim text.