US 2019/0198110 A1 · SEMICONDUCTOR APPARATUS

Abstract

A semiconductor apparatus may include a unit memory region, a first column main decoder, a second column main decoder, and a control circuit. The unit memory region may include a plurality of sub-memory regions. The first and second column main decoders may be configured to receive and decode a column pre-decoding signal and configured to generate a respective column select signal for controlling a column access of a respective first and second half of the plurality of sub-memory regions. The control circuit may be configured to provide the column pre-decoding signal to the first or second column main decoders based on their proximities to a sub-memory region to be enabled among the plurality of sub-memory regions.

Claims16

Dependent claims

A semiconductor apparatus comprising:

a unit memory region including a plurality of sub-memory regions;
a first column main decoder configured to receive and decode a column pre-decoding signal and configured to generate a first column select signal for controlling a column access of a first half of the plurality of sub-memory regions;
a second column main decoder configured to receive and decode the column pre-decoding signal and configured to generate a second column select signal for controlling a column access of a second half of the plurality of sub-memory regions;
and
a control circuit configured to provide the column pre-decoding signal to either the first column main decoder or the second column main decoder based on proximities, of the first column main decoder and the second column main decoder, to a sub-memory region to be enabled among the plurality of sub-memory regions.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor apparatus

Life of this patent

Semiconductor apparatus

Life of this patent

Abstract

Claims16