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US 2019/0198108 A1Published application
Parallel-connected merged-floating-gate nfet-pfet eeprom cell and array
AssigneeInternational Business Machines Corporation
InventorsTak Ning, Jeng-Bang Yau
Life of this patent
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Abstract
A shared floating gate device, the device including an. nFET, a pFET including a different material than that of the nFET, and a floating gate.
Claims19
A device, comprising;
- an nFET;
- a pFET ;
- and
- a floating gate,
- wherein the nFET and the pFET share floating gate.
2 more elements
An electrically erasable programmable read-only memory (EEPROM) cell, the cell comprising:
- an nFET;
- a pFET;
- and
- a floating gate,
- wherein the NFET and the pFET share the floating gate.
2 more elements
An array structure, comprising:
- a plurality of cells, each cell including:
- an nFET;
- a pFET;
- a floating gate;
- and
- an nFET access transistor including a drain connected to a source of the nFET and a drain of the pFET.
3 more elements
Dependencies are inferred from the claim text.