Forming structure and method for integrated circuit memory

An integrated circuit, comprising:

• a set of pads configured for connection to external circuits;
• a memory array including a plurality of banks of memory cells, each bank including a set of N access lines, configured as one of bit lines and word lines, and connected in current flow communication to memory cells in the bank;
• peripheral circuits coupled to pads in a signal subset of the set of pads, and to the plurality of sets of N access lines, the peripheral circuits including a control circuit configured to execute memory operations;
• a power rail coupled to at least one pad in a power supply subset of the set of pads by which power is distributed to the memory array and the peripheral circuits for the memory operations;
• a set of forming voltage rails having N members;
• and
• a plurality of sets of diodes, each set of diodes in the plurality of sets of diodes coupled to a corresponding bank in the plurality of banks, each set of diodes in the plurality of sets of diodes having N members, the N members in each of the sets of diodes being connected in current flow communication with corresponding ones of the N members of the set of forming voltage rails and with corresponding ones of the N access lines in its corresponding bank;
• and
• a set of switches having N members, switches in the set having a first terminal in current flow communication with a forming voltage pad in the set of pads, and a second terminal in current flow communication with a corresponding forming voltage rail in the set of forming voltage rails, the switches configured to electrically connect and disconnect the forming voltage pad and their corresponding forming voltage rails in response to a control sequence.

A method, comprising:

• providing an integrated circuit, the integrated circuit having a memory array including a plurality of memory cells, a plurality of access lines connected in current flow communication to memory cells in the array, and a forming voltage pad in current flow communication via diodes with access lines in the plurality of access lines;
• and
• applying forming pulses to the forming voltage pad using an external power source, the forming pulses having a voltage magnitude to forward bias the diode;
• and
• controlling switches on the integrated circuit according to a control sequence including connecting forming voltage rails connected to the forming voltage pad in sequence to memory cells via the corresponding ones of the plurality of access lines.