Auto-referenced memory cell read techniques

A method, comprising:

• applying an activation voltage to a memory array to activate a group of memory cells of the memory array;
• determining, at a first time, that a first set of memory cells has been activated based at least in part on applying the activation voltage;
• maintaining application of the activation voltage for a duration after the first time;
• and
• reading, after an end of the duration, a logic state of a second set of memory cells that includes the first set of memory cells.

An electronic memory apparatus, comprising:

• a memory medium;
• and
• a controller coupled with the memory medium, wherein the controller is operable to:
• receive a first set of bits of an input vector from a host device;
• compare at least a portion of the first set of bits that have a first logic value to a threshold stored at the controller;
• allocate a block of memory of the memory medium to store one or more bits and the first set of bits based at least in part on the comparing;
• generate a second set of bits that comprises at least some of the first set of bits and the one or more bits;
• and
• initiate storing the generated second set of bits in the block of memory.

An electronic memory apparatus, comprising:

• a memory array;
• and
• a controller in electronic communication with the memory array, wherein the controller is operable to:
• apply an activation voltage to the memory array to activate a group of memory cells of the memory array;
• determine, at a first time, that a first set of memory cells has been activated based at least in part on applying the activation voltage;
• maintain application of the activation voltage for a duration after the first time;
• and
• read, after an end of the duration, a logic state of a second set of memory cells that includes the first set of memory cells.